BLOCK0 data register 1.
RD_DIS | Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. |
USB_DEVICE_EXCHG_PINS | Enable usb device exchange pins of D+ and D-. |
USB_OTG11_EXCHG_PINS | Enable usb otg11 exchange pins of D+ and D-. |
DIS_USB_JTAG | Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. |
POWERGLITCH_EN | Represents whether power glitch function is enabled. 1: enabled. 0: disabled. |
DIS_USB_SERIAL_JTAG | Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. |
DIS_FORCE_DOWNLOAD | Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. |
SPI_DOWNLOAD_MSPI_DIS | Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download. |
DIS_TWAI | Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. |
JTAG_SEL_ENABLE | Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. |
SOFT_DIS_JTAG | Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. |
DIS_PAD_JTAG | Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. |
DIS_DOWNLOAD_MANUAL_ENCRYPT | Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. |
USB_DEVICE_DREFH | USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV |
USB_OTG11_DREFH | USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV |
USB_PHY_SEL | TBD |
KM_HUK_GEN_STATE_LOW | Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. |